CS6303 COMPUTER ARCHITECTURE Syllabus Semester III IT BTECH Anna University-Regulation-2013

CS6303                                          COMPUTER ARCHITECTURE                                         L  T  P C
3 0  0 3
OBJECTIVES:

• To make students understand the basic structure and operation of digital computer.
• To understand the hardware-software interface.
• To familiarize the students with arithmetic and logic unit and implementation of fixed point and floating-point arithmetic operations.
• To expose the students to the concept of pipelining.
• To familiarize the students with hierarchical memory system including cache memories and virtual memory.
• To expose the students with different ways of communicating with I/O devices and standard I/O

interfaces.

UNIT I             OVERVIEW & INSTRUCTIONS                                                                                    9
Eight ideas – Components of a computer system – Technology – Performance – Power wall –
Uniprocessors to multiprocessors; Instructions – operations and operands – representing instructions
– Logical operations – control operations – Addressing and addressing modes.

UNIT II          ARITHMETIC OPERATIONS                                                                                           7
ALU - Addition and subtraction – Multiplication – Division – Floating Point operations – Subword parallelism.

UNIT III        PROCESSOR AND CONTROL UNIT                                                                             11
Basic MIPS implementation – Building datapath – Control Implementation scheme – Pipelining –
Pipelined datapath and control – Handling Data hazards & Control hazards – Exceptions.

UNIT IV       PARALLELISM                                                                                                                  9
Instruction-level-parallelism – Parallel processing challenges – Flynn's classification – Hardware multithreading – Multicore processors

UNIT V       MEMORY AND I/O SYSTEMS                                                                                           9
Memory hierarchy - Memory technologies – Cache basics – Measuring and improving cache performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts, I/O processors.


OUTCOMES:
At the end of the course, the student should be able to:

• Design arithmetic and logic unit.
• Design and anlayse pipelined control units
• Evaluate performance of memory systems.
• Understand parallel processing architectures.

TOTAL: 45 PERIODS


TEXT BOOK:

35

1. David A.  Patterson  and  John  L.  Hennessey,  “Computer  organization  and  design?, Morgan

auffman / lsevier, Fifth edition, 2014.

REFERENCES:

1. V.Carl  Hamacher,  Zvonko  G.  Varanesic  and  Safat  G.  Zaky,  “Computer  Organisation“,

VI edition, McGraw-Hill Inc, 2012.

2. William Stallings “Computer Organization and Architecture”, Seventh Edition, Pearson

Education, 2006.

3. Vincent P.  Heuring,  Harry  F.  Jordan,  “Computer  System  Architecture”,  Second  Edition, Pearson Education, 2005.
4. Govindarajalu, “Computer Architecture and Organization, Design Principles and Applications",

first edition, Tata McGraw Hill, New Delhi, 2005.

5. John P. Hayes, “Computer Architecture and Organization”, Third Edition, Tata McGraw Hill,

1998.

6. http://nptel.ac.in/.

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