VL25402 Digital VLSI Design – Semester IV – VLSI – R-2025

Subject Code & Name: VL25402 – Digital VLSI Design

Regulation: R-2025

Semester: IV (Fourth Semester)

Branch: B.E. Electronics Engineering (VLSI)

Credits / L-T-P: 3 Credits | L-T-P: 3-0-0

Course Objectives

• The course aims to impart foundational knowledge on IC design abstraction levels, CMOS fabrication processes, and ASIC/FPGA design flows.
• It enables students to analyze the behavior of MOS transistors, explore various CMOS logic styles, and apply low-power design techniques.
• Additionally, the course develops competency in memory design, physical layout, and the implementation of arithmetic sub-systems in VLSI, equipping students with essential skills for advanced integrated circuit design.

Full Unit-wise Syllabus

Unit I – IC Design Flow Overview and Manufacturing of CMOS Integrated Circuits

Design abstraction levels in digital circuits - Issues in Digital Integrated Circuit Design - Quality Metrics of a Digital Design - ASIC Design Flow: Full Custom and Semi-custom Approach – FPGA Design flow – Difference between ASIC and FPGA - Silicon Semiconductor technology: The Silicon Wafer - Photolithography - Some Recurring Process Steps - Simplified CMOS Process Flow

Design Flow Explorer Activity: Develop a Comparative Flowchart of Full Custom, Semi-Custom, and FPGA design methodologies, including EDA Tool Mapping for each step.

Unit II – Fundamentals of MOS Transistors & CMOS Inverter Characteristics

Basic MOS transistors: Symbols, Enhancement mode - Depletion mode transistor operation - Regions of operation – Non-Ideal I-V Characteristics - CMOS inverter: DC Characteristics - Noise Margin – Switching Characteristics – Transistor Sizing - Static & Dynamic Power Dissipation

Seminar: Summary of MOSFET Operation and Characteristics - Understanding of Static and Dynamic Power Dissipation

Unit III – Logic Styles and Low Power Designs

Static CMOS Design - Pseudo-nMOS Logic- Cascode Voltage Switch Logic (CVSL) - Pass-Transistor Logic – Transmission Gate - Dynamic CMOS Design: Basic Principles - Domino logic - Power Logic Design Techniques:Reduction of Voltage Swing – Reduction of Switching Activity - Power Management Basic Techniques: Clock Gating - Power Gating

CMOS Logic Styles – A Practical Design Project: Use any EDA tools to compare Area, Power, and Delay of any Gates or any combinational circuits implemented using Static CMOS, Pass Transistor, Dynamic, Domino, and CVSL logic. Suggest which logic style suits different applications based on the results.

Unit IV – Semiconductor Memories and Physical Design

Conventional CMOS Latches – CMOS D Flip Flop – SDFF – TSPC Flip Flop – 6T SRAM –SRAM Array - 1T DRAM – CAM Physical Design: Stick Diagrams - Layout Design Rules – Layout Design of Digital Logic.

Draw Your Chip Activity: Draw the Schematic, Stick Diagrams, and Layout of basic CMOS Logic Gates (or) Universal logic gates or Memory Element. Use color sketches on an A3 sheet and submit them as a report.

Unit V – VLSI Sub-System Design

Adders: Ripple Carry Adder - Carry Look Ahead Adder - Carry Skip Adder - Carry Select Adder - Multipliers: Unsigned Array Multiplier – Two’s Complement Signed Multiplier- Booth Encoding Multiplier

VLSI Arithmetic Activity: Consider any two (A & B) 8-bit data, 1. Add A and B using:Ripple Carry Adder and Carry Select Adderby hand. 2. Multiply A and B using the Array Multiplier and Booth Encoding method by hand. Submit a report with step-by-step solutions, the Architecture required for solving the problem, and a brief discussion on trade-offs in terms of delay, area, and power.

Course Outcomes (COs)

• CO1: Understand IC design flow and CMOS fabrication process.
• CO2: Design MOS circuits and analyze the factors influencing the operation of CMOS transistors
• CO3: Design a semiconductor memory and the physical layout of the digital logic
• CO4: Design and optimize arithmetic subsystems such as adders and multipliers using VLSI techniques
• CO5: Analyze the speed, power, and area trade-offs of different circuit families for combinational logic and sequential logic

Assessment Pattern (Quick Note)

• Weightage: Continuous Assessment 40% | End Semester Examinations 60%
• Internal methodology: Assignment (20%), Software activity (20%), Quiz (20%), Internal Examinations (40%).

Source: Official Anna University – B.E. Electronics Engineering (VLSI Design and Technology) R-2025 Syllabus
Last Updated: October 2026