EI25C08 Digital System Design and Applications – Semester IV – EIE / ICE – R-2025

Subject Code & Name: EI25C08 – Digital System Design and Applications

Regulation: R-2025

Semester: IV (Fourth Semester)

Branch: B.E. Electronics and Instrumentation Engineering (EIE) / B.E. Instrumentation and Control Engineering (ICE)

Credits / L-T-P: 3 Credits | L-T-P: 3-0-0

Course Objectives

• This course introduces number systems, Boolean algebra, and gate-level minimization for digital logic design.
• It emphasizes the design and analysis of combinational and sequential logic circuits including both synchronous and asynchronous types.
• It also covers programmable logic devices, digital simulation, and VHDL-based implementation for practical applications.

Full Unit-wise Syllabus

Unit I – Boolean Algebra and Gate Level Minimization

Review of number systems, types and conversion, binary codes, error detection and correction codes (Parity and Hamming code). Boolean theorems and properties, Boolean functions, logic gates. Gate-level minimization using Karnaugh Map, SOP & POS simplification, Don't care conditions. Implementations of logic functions using gates – NAND, NOR implementations.

Unit II – Combinational Logic

Design of adders, subtractors, multiplexers. Combinational logic design using multiplexers. Demultiplexers and their use in combinational logic design. 2-bit magnitude comparator, code converters – BCD to Binary and Binary to BCD, encoder, priority encoder – Decimal to BCD, Octal to Binary, decoders – BCD to Decimal and BCD to Seven Segment Display Decoder.

Unit III – Synchronous Sequential Logic

Sequential logic – SR, JK, JKMS, D and T flip-flops, characteristics and excitation table, level triggering and edge triggering, counters – asynchronous and synchronous type, modulo counters, shift registers. Design of synchronous sequential circuits – Moore and Mealy models, state diagram, state reduction, state assignment.

Unit IV – Asynchronous Sequential Circuits

Asynchronous sequential logic circuits – transition and flow table, race conditions, hazards, and errors in digital circuits, analysis of asynchronous sequential logic circuits.

Unit V – Memory and Logic Families

Memories: PROM, PLA, PAL, CPLD, FPGA. Digital logic gate realization and characteristics of TTL, ECL, and CMOS families.

Unit VI – VHDL

RTL Design – combinational logic, sequential circuit, operators. Introduction to packages, subprograms, testbench. (Simulation/Tutorial Examples: adders, counters, flip-flops, multiplexers & demultiplexers)

Tasks

T1:Apply mathematical knowledge of number systems, Boolean expressions/functions to simplify and realize logical expressions. T2:Design and verify combinational logic circuits T3:Design and verify synchronous sequential logic circuits. T4:Analyze and design asynchronous sequential logic circuits. T5:Understand memory types and gain knowledge on building blocks of different Programmable Logic devices and make use of appropriate software such as VHDL for electronic prototyping and modeling of digital systems.

Course Outcomes (COs)

• CO1: Explain number systems, binary codes, Boolean algebra, logic gates, and gate-level minimization techniques including SOP, POS, K-Map simplification, and NAND/NOR realizations.
• CO2: Design and analyze combinational logic circuits including adders, subtractors, multiplexers, demultiplexers, encoders, decoders, and code converters.
• CO3: Design, simulate, and implement synchronous sequential circuits including flip-flops, counters, shift registers, and sequence detectors using Moore and Mealy models.
• CO4: Analyze and design asynchronous sequential circuits, identify race conditions, hazards, and errors, and implement solutions for reliable operation.
• CO5: Apply VHDL for RTL design and simulation of combinational and sequential circuits, including testbench creation, and implement memory and programmable logic devices (PLA, PAL, CPLD, FPGA) in practical applications.

Assessment Pattern (Quick Note)

• Weightage: Continuous Assessment 40% | End Semester Examinations 60%
• Internal methodology: Assignments (20%), Solution to application-oriented problems using software (20%), Review of GATE questions (20%), Internal Examinations (40%)

Source: Official Anna University – B.E. Electronics and Instrumentation Engineering R-2025 Syllabus
Last Updated: October 2026