VL25303 Digital Logic Design Laboratory – Semester III – VLSI – R-2025

Subject Code & Name: VL25303 – Digital Logic Design Laboratory

Regulation: R-2025

Semester: III (Third Semester)

Branch: B.E. Electronics Engineering (VLSI)

Credits / L-T-P: 2 Credits | L-T-P: 0-0-4

Course Objectives

• This course aims to build a strong foundation in understanding and applying logic gates for digital circuit design.
• It emphasizes the design of advanced combinational and sequential logic circuits, leading to the development of practical sequential applications.
• Additionally, students will gain hands-on experience in Verilog HDL programming and enhance their problem-solving abilities through project-based learning.
• Implementation of a binary adder and subtractor using logic gates. 1.
• Design and implementation of odd/even parity generator and checker using logic gates 2.
• Design and implementation of code converters using logic gates. • Binary to gray • Binary to BCD 3.
• Design and implementation of a 2-bit magnitude comparator using logic gates. 4.
• Design and implementation of Multiplexer& Demultiplexer using logic gates 5.
• Design and implementation of encoder & decoder using logic gates 6.
• Implementation of the given gates and simple Boolean functions using Multiplexers and Decoders. 7.
• Construct a NAND and NOR SR Latch using logic gates. 8.
• Construct a D and JK flip-flop using logic gates. 9.
• Conversion of one flip-flop into another flip-flop. 10.
• Design a Prescaler circuit using flip-flops 11.
• Design and implementation of Shift register (SISO, SIPO,PIPO) using flip-flops 12.
• Design and implementation of up and down counters using flip-flops

Full Unit-wise Syllabus

List of Experiments

• Implementation of a binary adder and subtractor using logic gates.
• Design and implementation of odd/even parity generator and checker using logic gates
• Design and implementation of code converters using logic gates.
• Binary to gray
• Binary to BCD
• Design and implementation of a 2-bit magnitude comparator using logic gates.
• Design and implementation of Multiplexer& Demultiplexer using logic gates
• Design and implementation of encoder & decoder using logic gates
• Implementation of the given gates and simple Boolean functions using Multiplexers and Decoders.
• Construct a NAND and NOR SR Latch using logic gates.
• Construct a D and JK flip-flop using logic gates.
• Conversion of one flip-flop into another flip-flop.
• Design a Prescaler circuit using flip-flops
• Design and implementation of Shift register (SISO, SIPO,PIPO) using flip-flops
• Design and implementation of up and down counters using flip-flops Programming using Verilog VHDL: a. Multiplexers & Demultiplexers b. Encoders and Decoders c. Flip-flops (SR, JK, T, D)

Activities: Design and build a digital system using combinational and sequential circuits (e.g., a digital stopwatch, a simple calculator, or a traffic light controller, etc.) Draw the block diagram of a simple RISC-V CPU. Select and design one of the blocks such as the Program Counter, Memory Address Register, RAM, or ALU etc.. Design of rolling display, Design of real time clock.

Course Outcomes (COs)

• CO1: Design and implement combinational logic circuits such as adders, subtractors, comparators multiplexers, encoders, decoders, and code converters using logic gates.
• CO2: Design and implement sequential logic circuits including latches, flip flops, counters, shift registers and their conversions using logic gates.
• CO3: Develop and simulate digital circuits using Verilog HDL for combinational and sequential modules such as MUX, DECODER, and flip flops.
• CO4: Design and implement project based digital systems such as counters, clocks, RISC V components, and real time applications using combinational and sequential logic.

Assessment Pattern (Quick Note)

• Weightage: Continuous Assessment 60% | End Semester Examinations 40%
• Internal methodology: Project (30%), Assignment (10%), Practical (30%), Internal Examinations (30%)

Source: Official Anna University – B.E. Electronics Engineering (VLSI) R-2025 Curriculum
Last Updated: September 2026

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