Subject Code & Name: VL25301 – Digital Logic Design
Regulation: R-2025
Semester: III (Third Semester)
Branch: B.E. Electronics Engineering (VLSI)
Credits / L-T-P: 3 Credits | L-T-P: 3-0-0
Course Objectives
- This course provides a comprehensive understanding of Boolean algebra and logic minimization techniques to optimize digital circuit designs.
- It covers the design and analysis of combinational and sequential circuits, including arithmetic units, multiplexers, encoders, flip-flops, counters, and shift registers.
- Students will also explore memory technologies, programmable logic devices, and implement digital systems using both synchronous and asynchronous methods with VHDL.
Full Unit-wise Syllabus
Unit I – Minimization Techniques and Logic Gates
Minimization Techniques: Boolean postulates and laws – De-Morgan‟s Theorem - Principle of Duality - Boolean expression - Minimization of Boolean expressions –– Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don‟t care conditions – Quine - Mc Cluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive–OR and Exclusive–NOR Implementations of Logic Functions using gates, NAND–NOR implementations – RTL, TTL, ECLand CMOS Logic and their characteristics – Tristate gates
Unit II – Combinational Circuits
Design procedure – Half adder – Full Adder – Half subtractor – Full subtractor – Parallel binary adder, parallel binary Subtractor – Fast Adder - Carry Look Ahead adder – Serial Adder/Subtractor - BCD adder – Binary Multiplier – Binary Divider - Multiplexer/ Demultiplexer – decoder - encoder – parity checker – parity generators – code converters - Magnitude Comparator.
Unit III – Sequential Circuits
Latches, Flip-flops - SR, JK, D, T, and Master-Slave – Characteristic table and equation –Application table – Edge triggering – Level Triggering – Realization of one flip flop using other flip flops – serial adder/subtractor- Asynchronous Ripple or serial counter – Asynchronous Up/Down counter - Synchronous counters – Synchronous Up/Down counters – Programmable counters – Design of Synchronous counters: state diagram- State table –State minimization –State assignment - Excitation table and maps-Circuit implementation - Modulo–n counter, Registers – shift registers - Universal shift registers – Shift register counters – Ring counter – Shift counters - Sequence generators.
Unit IV – Memory Devices
Classification of memories – ROM - ROM organization - PROM – EPROM – EEPROM – EAPROM, RAM – RAM organization – Write operation – Read operation – Memory cycle - Timing wave forms – Memory decoding – memory expansion – Static RAM Cell- Bipolar RAM cell – MOSFET RAM cell – Dynamic RAM cell –Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) – Field Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using ROM, PLA, PAL
Unit V – Synchronous and Asynchronous Sequential Circuits
Synchronous Sequential Circuits: General Model – Classification – Design – Use of Algorithmic State Machine – Analysis of Synchronous Sequential Circuits Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits – Incompletely specified State Machines – Problems in Asynchronous Circuits – Design of Hazard Free Switching circuits. Design of Combinational and Sequential circuits using VHDL/Verilog.
Course Outcomes (COs)
- CO1: Explain Boolean algebra laws, logic gates, and minimization techniques for digital circuits.
- CO2: Apply knowledge of logic families and programmable logic devices (PROM, PLA, PAL) for implementing digital systems and memory elements.
- CO3: Design and analyze combinational circuits and sequential circuits.
- CO4: Analyze asynchronous sequential circuits, identify hazards and design race free and hazard free circuits.
- CO5: Evaluate the performance of digital circuits considering propagation delay, power consumption, and noise margins and communicate results effectively while working in teams with ethical and societal awareness.
Assessment Pattern (Quick Note)
- Weightage: Continuous Assessment 40% | End Semester Examinations 60%
- Internal methodology: Assignment (20%), Software activity (20%), Quiz (20%), Internal Examinations (40%). CO Course Outcome PO PSO
Source: Official Anna University – B.E. Electronics Engineering (VLSI) R-2025 Curriculum
Last Updated: September 2026
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