IT25202 Digital Principles and System Design – Semester II – IT – R-2025

Subject Code & Name: IT25202 – Digital Principles and System Design

Regulation: R-2025

Semester: II (Second Semester)

Branch: B.Tech. IT (IT)

Credits / L-T-P: 4 Credits | L-T-P: 3-0-2

Course Objectives

• To understand the basics of number systems and Boolean algebra.
• To learn how to design and analyze combinational and sequential logic circuits.
• To use hardware description languages (HDL) for implementing digital systems.

Full Unit-wise Syllabus

Unit I – Boolean Algebra

Number Systems, Binary, Octal, Hexadecimal, Representation of negative numbers, 1’s and 2s Complements, Arithmetic Operations, Binary Codes. Boolean Algebra, Theorems and Postulates, Functions, Truth Table, Logic Gates, Universal gates.

Practical: Simple functions using gates; Implementation of Boolean functions.

Unit II – Canonical Functions

Canonical and Standard Forms, Minterms and Maxterms, Sum of Products and Product of Sums, Conversions and Expansion.

Practical: Simplification and expansion of standard Boolean functions.

Unit III – Karnaugh Map and Combinational Logic

Simplification of Boolean Functions, Karnaugh Map, 2,3,4 variables, NAND / NOR Implementations, Combinational Circuits, Arithmetic Circuits, Half and Full Adders, Subtractors. Introduction to HDL.

Practical: Implementation of combinational circuits using gates for arbitrary functions; Implementation of Arithmetic circuits and extended operations.

Unit IV – Combinational Logic Design

Binary Parallel adder, Carry Look-ahead Adder, BCD Adder, Binary multiplier, Magnitude Comparator, Code Converters, Decoder, Encoder, Priority Encoder, Mux/Demux, Applications, Introduction to HDL and HDL for these circuits.

Practical: Combinational circuits using code converters; BCD adder, encoder and decoder circuits.

Unit V – Sequential Logic Design

R – S Latch, D Latch, Flip flops, SR, JK, T, D, Master /Slave Flip Flop, Flip flop excitation tables, Analysis of clocked sequential circuits, Moore /Mealy models, Registers, Shift Registers, Universal Shift Register. Counters, Asynchronous Ripple Counters, Synchronous Counters – Ring Counter, Johnson Counter.

Practical: Design of a digital circuit for solving practical problems.

Unit VI – System Design

Memory Systems, RAM, ROM, Memory Decoding, error detection and correction, Digital System Design using PROM, PLA, PAL, FPGA.

Activities: Combination of in class & Flipped.

Practical: Project demonstration and presentation; Mini project on the design of a digital circuit for solving practical problems.

Course Outcomes (COs)

• CO1: Identify number systems and basic logic gates.
• CO2: Apply Boolean algebra and Karnaugh maps to simplify and implement combinational logic circuits.
• CO3: Design and analyze digital systems with sequential components using HDL and hardware tools.
• CO4: Explore modern tools and resources to keep learning about digital system design.

Assessment Pattern (Quick Note)

• Weightage: Continuous Assessment 40% | End Semester Examinations 60%
• Internal methodology: Assignments (10%), Quiz (5%), Project based learning (20%), Flipped Classroom (5%), Review of GATE questions (10%) & Internal Assessment 50%

Source: Official Anna University – B.Tech. Information Technology R-2025 Syllabus
Last Updated: September 2026