EC25C07 Digital System Design – Semester III – ECE / ElecComp – R-2025

Subject Code & Name: EC25C07 – Digital System Design

Regulation: R-2025

Semester: III (Third Semester)

Branch: B.E. Electronics and Communication Engineering (ECE) / B.E. Electronics and Computer Engineering (ElecComp)

Credits / L-T-P: 3 Credits | L-T-P: 3-0-0

Course Objectives

• This course aims to create a strong foundation for Digital Electronics.
• The students are taught the basic components of digital systems and the processes of their implementation.
• The students are also taught Boolean algebra, logic gates, the basics of memories, and the implementation of combinational and sequential digital circuits using logic gates.
• Students are trained to employ the principles of digital electronics to implement digital design for the given problem.

Full Unit-wise Syllabus

Unit I – Boolean Algebra

Revisiting Boolean algebra and minimization, 4-variable Karnaugh Maps, SOP and POS Minimization using Karnaugh Maps-Introduction to Verilog HDL, Data Types and Operators-Different types of Modeling

Unit II – Combinational Digital Circuits

Introduction to combinational circuits, realization of logic expressions using AOI, NOR, and NAND gates. Adders, Subtractors, Multiplexers, De-multiplexers, Encoders, Decoders, Priority encoders, Arithmetic circuits, such as multipliers, Ripple adders, Code-converters Programming using Verilog HDL.

Unit III – Sequential Digital Circuits

Introduction to sequential circuits, Moore and Mealy machine, Flip-flops and Latches, realization of flip-flops using S-R flip-flop, master slave flip-flop, JK flip-flop, T and D flip- flops, Realization of flip-flops using logic gates, introduction to shift registers, realization of different types of shift registers, introduction to counters, realization of different types of counters, Introduction to different types of memories Programming using Verilog HDL.

Unit IV – Finite State Machines

Need for FSM, Elements of FSM, Components in FSM, FSM in HDL, Issues in FSM design, Case studies: Sequence detector, Odd parity Checker, Vending Machine

Unit V – FPGA Architecture

Introduction to FPGA Architecture, Components of FPGA Architectures – Programming Technologies, Logic elements and Look-up Tables, Dedicated multipliers, Distributed RAM, Shift registers, Digital Clock Managers, Altera FPGA and AMD Xilinx FPGA architectures and design flow-AMD Spartan, Virtex, Altera Cyclone, Arria and Agilex architectures-Introduction to IP Cores- AMD Microblaze V and Altera NIOS V Soft core processors

Course Outcomes (COs)

• CO1: Explain fundamental concepts of digital electronics including Boolean algebra, logic gates, and digital circuit classifications.
• CO2: Apply logic design techniques and minimization methods to develop optimized solutions for digital circuits. Analyze practical problems and design appropriate.
• CO3: Digital solutions using components such as multiplexers, encoders, latches, counters, and code converters.
• CO4: Develop and verify digital circuit designs using digital trainer kits and Hardware Language (HDL) programming.

Assessment Pattern (Quick Note)

• Weightage: Continuous Assessment 40% | End Semester Examinations 60%
• Internal methodology: Assignment (20%), Software activity (20%), Quiz (20%), Internal Examinations (40%)

Source: Official Anna University – B.E. Electronics and Communication Engineering R-2025 Curriculum
Last Updated: September 2026