Subject Code & Name: CS25C06 – Digital Principles and Computer Organization
Regulation: R-2025
Semester: II (Second Semester)
Branch: B.E. CSE (CSE)
Credits / L-T-P: 4 Credits | L-T-P: 3-1-0
Course Objectives
- To impart knowledge on digital logic and provide functional concepts of computer systems with necessary illustrations.
Full Unit-wise Syllabus
Unit I – Digital Logic
Digital Systems, Integer Arithmetic, Addition and Subtraction of Signed Numbers, Boolean Algebra, Theorems and Postulates, Functions, Truth Table, Canonical and Standard Forms, Simplification using K-Maps, Digital Logic Gates, Universal gates, Implementation of Logic Gates, Integrated Circuits.
Activities: Assignment on Karnaugh Map; Build logic circuits; Virtual demonstration of logical gates.
Unit II – Computer System
Basic structure of a computer, Classes of Computer, Functional units – Interconnection of components, Von Neumann architecture and Harvard architecture – Instruction execution cycle, Performance metrics: MIPS, MFLOPS, CPI, throughput.
Activities: MIPS, MFLOPS, and CPI calculations; Preparations of report on comparison of two CPU from different manufacturing.
Unit III – Arithmetic and Logic Unit
Combinational Circuits: Adders, Binary Adder, Binary Parallel Adder, Subtractor, Multiplexers, Decoders, Design of Fast Adder, Multiplication of Signed and Unsigned Numbers, Fast Multiplication – Integer Division, Floating Point Numbers and Operations, Booth’s algorithm for signed multiplication, Sequential Circuits: Flip-Flops, Registers, Counters.
Activities: Virtual demonstration on Binary adder; Build a parallel adder.
Unit IV – Processing and Pipelining
Instruction Set Architecture: RISC vs CISC, Addressing modes, Hardwired control and Micro programmed control unit, Concepts of Pipelining, Pipeline stages and Timing diagram, Hazards: Structural, Data and Control Hazards, Instruction-level parallelism, Parallel processing concepts: SIMD, MIMD, Superscalar processors, Vector and Array Processor.
Activities: Comparison of RISC-V and x86 ISAs; present findings on their relevance to AI accelerators; Spot and resolve different types of pipeline hazards in given scenarios.
Unit V – Memory
Memory hierarchy: Registers, Cache, Main Memory – RAM – ROM: PROM, EPROM, EEPROM – Secondary storage, HDD, SSD, Cache Organization, Cache replacement policies, NUMA – DMA – ECC.
Unit VI – I/O Systems
I/O Techniques: Programmed, Interrupt-Driven, DMA, I/O Devices and Interface Standards: PCI, USB, SATA, Interrupt Types and Priority Handling, Buses and Bus Arbitration, Peripheral Communication.
Activities: Virtual demonstration of DMA; I/O in Real AI Systems.
Course Outcomes (COs)
- CO1: Identify basic digital components and their functions in a computer system.
- CO2: Apply Boolean algebra and number systems to design simple digital circuits and simulate them using tools.
- CO3: Analyze instruction sets, arithmetic units, and performance metrics to evaluate processor design.
- CO4: Engage in continuous learning to update with advancements through evolving computing trends.
Assessment Pattern (Quick Note)
- Weightage: Continuous Assessment 40% | End Semester Examinations 60%
- Internal methodology: Quiz (5%), Assignments (10%), Flipped Classroom (5%), Project (20%), Review of GATE questions (10%) & Internal Assessment (50%)
Source: Official Anna University – B.E. Computer Science and Engineering R-2025 Syllabus
Last Updated: September 2026
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